SLE5536/36E | SLE5536S/36SE | SLE5542 | SLE55R01 | SLE55R02 | SLE55R08 | SLE55R16
Intelligent 221–Bit EEPROM Counter
for > 20000 Units with Security Logic
and High Security Aithentication
Datasheet : SLE5536 36E.pdf
Features
- 221 bit EEPROM and 16 bit mask-programmable ROM
- 104 bit user memory fully compatible with SLE 4406/06E
- 64 bit Identification Area consisting of
- 16 bit Manufacturer code (mask-programmable ROM)
- SLE 5536E:
- 8 bit Manufacturer data, card issuer dependent (ROM)
- 40 bit for personalization data of card issuer (PROM)
- SLE 5536SE:
- 48 bit for personalization data of card issuer (PROM)
- –40 bit Counter Area including 1 bit of personalization (PROM/EEPROM)
- 64 bit Identification Area consisting of
- 133 but additional memory for advance features
- 4 bit Counter Backup (anti-tearing flags)
- 1 bit initiation flag for Authentication Key 2
- 16 bit Data Area 1 for free user access
- 48 bit Authentication Key 1
- either 48 bit Data Area 2 for user defined data or 48 bit Authentication Key 2
- 16 bit Data Area 3 from free user access
- 104 bit user memory fully compatible with SLE 4406/06E
- Counter with up to 33352 count units fully compatible with SLE 4406/06E
- Five stage abacus counter
- Due to testing purpose a maximum of 21064 counts units is guaranteed
- Counter tearing protection
- Backup feature activated at choice
- Counter tearing protection may be disabled by mask option
- High security authentication unit
- individual card authentication fully compatible with SLE 4436/36E
- Random number as challenge
- Individual secret Authenticaton Key 1
- Optional individual secret Authenticaton Key 2
- Calculation of up to 16 bit response
- Calculation of a 16 bit response within 30 ms at a clock frequency of 100 kHz optional activation of response calculation with cipher block chaining
- Certification of the counter value
- individual card authentication fully compatible with SLE 4436/36E
- Transport Code protection for delivery
- EEPROM security cells in sensitive areas
- Chip circuitry and chip layout optimised for high security against physical and electrical signal analysis