P5CD072 | P5CT072 | P5SC036
Datasheet: P5SC036.pdf
[NDA with NXP is required for this datasheet.
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Product Specific Features
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36 Kbytes EEPROM (including 192 bytes reserved manufacturer/security area)
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96 Kbytes User ROM
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2304 bytes RAM
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256 bytes + 2 Kbytes CXRAM
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Security Features
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Enhanced Security Sensors
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Low / high clock frequency sensor
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Low / high temperature sensor
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Single Fault Injection (SFI) attack detection
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Light sensors
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Electronic fuses for safeguarded mode control
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Unique ID for each die
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Clock Input Filter for protection against spikes
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Power-up / Power-down reset
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Optional programmable “Card Disable” feature
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Memory Security (encryption and physical measures) for RAM, EEPROM and ROM
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Memory protection (encryption and physical measures) for RAM, EEPROM and ROM
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Optional disabling of ROM read instructions by code executed in EEPROM
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Optional disabling of any code execution out of RAM
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EEPROM programming:
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No external clock
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Hardware sequencer controlled
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On-chip high voltage generation
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Enhanced error correction mechanism
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64 or 128 EEPROM bytes for customer-defined Security FabKey. Featuring batch-, wafer- or die-individual security data, incl. encrypted diversification features on request
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14 bytes User Write Protected Security area in EEPROM (byte access, inhibit functionality per byte)
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32 bytes Write Once Security area in EEPROM (bit access)
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32 bytes User Read Only area in EEPROM (byte access)
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Customer specific EEPROM initialization optional
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High speed DES-3 co-processor (64 bit parallel processing DES engine)